CoWoS-S
CoWoS-S is the original Chip-on-Wafer-on-Substrate packaging · used on H100, A100 · being phased out for CoWoS-L in 2025-26.
CoWoS-S is the original Chip-on-Wafer-on-Substrate packaging · used on H100, A100 · being phased out for CoWoS-L in 2025-26.
Basic
CoWoS-S is TSMC's first-gen advanced packaging for AI. Used on NVIDIA A100, H100, AMD MI300X early production, and others. Supports 6-8 HBM stacks per package. Being supplanted by CoWoS-L which supports larger interposers + more HBM. TSMC is gradually reallocating CoWoS-S capacity to CoWoS-L.
Deep
CoWoS-S uses a monolithic silicon interposer (reticle-size limited) vs CoWoS-L's Local Silicon Interconnect bridges. This limits package size and HBM count per chip. H100 with 80GB HBM3 is near the upper limit for CoWoS-S. Still used heavily in 2025-26 for H100 production; TSMC splits capacity between S and L based on customer demand.
Expert
CoWoS-S production is flat to declining as TSMC shifts capacity. Some chips (B100, lower-tier ASICs) still use CoWoS-S. The technology will persist for mid-tier AI chips through 2027. Yield on CoWoS-S is mature and high · unlike CoWoS-L which still ramps. Supply-chain players: TSMC (fab), Ibiden (substrate), ASE/Amkor (final assembly).
Depending on why you're here
- ·1st-gen advanced packaging · monolithic interposer
- ·Used on A100, H100, MI300X early
- ·Being phased out for CoWoS-L
- ·H100 availability ultimately tied to CoWoS-S capacity
- ·Shift to CoWoS-L impacts H100 pricing
- ·Watch TSMC capacity allocation
- ·Declining allocation · CoWoS-L takes priority
- ·Mature yield · lower cost than CoWoS-L
- ·Mid-tier AI chips will use CoWoS-S through 2027
- ·The older way TSMC packages AI chips
- ·Used for H100 · still the most common AI chip
- ·Being replaced by a newer method (CoWoS-L)
CoWoS-S is the fading standard · understanding the transition to CoWoS-L explains AI chip supply dynamics.