Every Foundry · Tracked

TSMC fabricates 90% of all AI chips tracked by BenchGecko. This includes NVIDIA's entire Blackwell and Hopper lineup, AMD's Instinct series, Google's TPUs, AWS Trainium, and Microsoft Maia. The dominance stems from TSMC's advanced nodes (N4/N5) and CoWoS packaging capacity.

CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's advanced packaging technology that connects GPU dies to HBM memory stacks via a silicon interposer. CoWoS-L capacity, not wafer output, is the binding constraint on AI chip supply. TSMC is aggressively expanding CoWoS capacity but demand from NVIDIA, AMD, and hyperscaler ASICs exceeds supply through 2026.

Yes, but at a cost. SMIC achieved a 7nm-equivalent node using DUV multi-patterning, which requires more lithography steps, lower yields, and higher costs per wafer. This is how Huawei's Ascend 910C is fabricated. A 5nm-equivalent attempt is reportedly in development but faces severe yield and cost challenges without EUV access.

Intel 18A is Intel Foundry's upcoming 1.8nm-equivalent node, featuring RibbonFET (Gate-All-Around transistors) and PowerVia (backside power delivery). It's critical for US semiconductor sovereignty and Intel's survival as a foundry. Microsoft is the first external customer. If 18A succeeds, it would give the US a leading-edge fab alternative to TSMC.

BenchGecko tracks 22 fab locations across 9 countries. These range from TSMC's N3-capable Fab 18 in Tainan to SMIC's sanctioned Shanghai facilities and Intel's CHIPS Act-funded Ohio mega-fab. Fab geography matters for supply chain resilience, export controls, and datacenter proximity.

Capacity utilization measures what percentage of a foundry's production capacity is in use. At 95%+ utilization, a foundry is effectively at capacity and new orders face long lead times. Currently, TSMC's advanced nodes run at 72% average utilization with packaging at 100%. This data comes from quarterly earnings disclosures.